1 / 3 www.asb.co.kr january 2010 p lerow tm ALUC1405B1 internally matched balanced lna module including coupler parameter unit specifications min typ max frequency range mhz 1030 1780 gain db 13.5 14.5 gain flatness db ? 0.5 ? 0.6 noise figure db 1.6 1.7 output ip3 (1) dbm 31 32 s11/s22 (2) db - 15/ - 15 output p1db dbm 18.5 19.5 switching time (3) ? sec - supply current ma 120 140 supply voltage v 5 impedance ? 50 max. rf input power dbm c.w 29~31(before fail) package type & size mm surface mount type, 21wx13lx5h operating temperature is C 40 ? c to +85 ? c. 1) oip3 is measured with two tones at an output power of +4 dbm/tone separated by 1 mhz. 2) s11, s22(max) is the worst value within the frequency band. 3) switching time means the time that takes for output power to get stabilized to its final level after switching dc voltage from 0 v to v s . port number function 2 rf in 7 rf out 6, 10 vs others, bottom gnd feature s s 21 = 27.2 db@1880 mhz = 26.8 db@1920 mhz nf of 0.65 db over fr e quency unconditionally stable single 5 v supply high oip3@low current 2 - stage balanced type specifications (in pr o duction) feature s s 21 = 15.5 db@1030 mhz = 14.5 db@1780 mhz nf of 1.6 db over fr e quency unconditionally stable single 5 v supply high oip3@low current 1 - stage balanced type c o u pl er website: www.asb.co.kr e - mail: sales@asb.co.kr tel: (82) 42 - 528 - 722 3 f ax : (82) 42 - 528 - 7222 more inform a tion c o u pl er c o u pl er c o u pl er c o u pl er specifications (in pr o duction) typ.@t = 25 ? c, v s = 5 v, freq. = 1405 mhz, z o.sys = 50 ohms note: 1. the number and size of ground via holes in a circuit board is critical for thermal rf grounding consider a tions. 2. we recommend that the ground v ia holes be placed on the bottom of all ground pins for better rf and thermal performance, as shown in the dra w ing at the left side. 1 - stage balanced type c o u p l e r c o u p l e r c o u pl er c o u pl er c o u pl er ou t line drawing (unit: mm) (top view) (bottom side view) (right side view) 1 3 7 5 8 4 al uc1405b1 2 6 solder stencil area ? 0.4 plated thru holes to ground plane (recommended footprint) 9 10
2 / 3 www.asb.co.kr january 2010 p lerow tm ALUC1405B1 internally matched balanced lna module including coupler description s - param e ters noise figure oip3 p1db 1030~1780 mhz +5 v typical pe rformance (measured) s - parameters & k fa c tor
3 / 3 www.asb.co.kr january 2010 p lerow tm ALUC1405B1 internally matched balanced lna module including coupler 1) the tantal or mlc (multi layer ceramic) capacitor is optional and for bypassing the ac noise introduced from the dc supply. the capacitance value may be determined by customer s dc supply status . the c a- pacitor should be placed as close as possible to v s pin and be connected directly to the ground plane for the best electrical performance . 2) dc blocking capacitors are always necessarily placed at the input and output port for allowing only the rf signal to pass and blocking the dc component in the signal. the dc blocking capacitors are inclu d- ed inside the aluc module. t herefore, c1 & c2 capacitors may not be necessary, but can be added just in case that the customer wants. the value of c1 & c2 is determined by considering the application fr e- quency. application circuit recommended soldering reflow process 20~40 sec 260 ? c 200 ? c 150 ? c 60~180 sec ramp - up (3 ? c/sec) ramp - down (6 ? c/sec) in out vs size 40 x 40 mm (for al uc series C 21 x 13 mm) evaluation board layout v s tantal or mlc (multi layer c e ramic) c a pacitor aluc out in c1 c2 + - + - tantal or mlc (multi layer c e ramic) c a pacitor v s vs
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